 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| STR71xF ARM7TDMITM 32-bit MCU with Flash, USB, CAN 5 timers, ADC, 10 communications interfaces Core - ARM7TDMI 32-bit RISC CPU - 59 MIPS @ 66 MHz from SRAM - 45 MIPS @ 50 MHz from Flash Memories - Up to 256Kbytes Flash program memory (10 kcycles endurance, 20 yrs retention) - 16K bytes Flash data memory (100 kcycles endurance, 20 yrs retention) - Up to 64 Kbytes RAM - External Memory Interface (EMI) for up to 4 banks of SRAM, Flash, ROM - Multi-boot capability Clock, Reset and Supply Management - 3.0 to 3.6V application supply and I/Os - Internal 1.8V regulator for core supply - Clock input from 0 to 16.5 MHz - Embedded RTC oscillator running from external 32 kHz crystal - Embedded PLL for CPU clock - Realtime Clock for clock-calendar function - 5 power saving modes: SLOW, WAIT, LPWAIT, STOP and STANDBY modes Nested interrupt controller - Fast interrupt handling with multiple vectors - 32 vectors with 16 IRQ priority levels - 2 maskable FIQ sources LQFP64 10 x 10 LQFP144 20 x 20 LFBGA64 8 x 8 x 1.7 LFBGA64 8 x 8 x 1.7 LFBGA144 10 x 10 x 1.7 5 Timers - 16-bit watchdog timer - 3 16-bit timers with 2 input captures, 2 output compares, PWM and pulse counter - 16-bit timer for timebase functions 10 Communications Interfaces - 2 I2C interfaces (1 multiplexed with SPI) - 4 UART asynchronous serial interfaces - Smart Card ISO7816-3 interface on UART1 - 2 BSPI synchronous serial interfaces - CAN interface (2.0B Active) - USB Full Speed (12Mbit/s) Device Function with Suspend and Resume - HDLC synchronous communications 4-channel 12-bit A/D Converter - Sampling frequency up to 1kHz - Conversion range: 0 to 2.5V Development Tools support STR711 FR2 256+16 64 STR712 FR0 64+16 16 STR712 FR1 128+16 32 CAN, 32 I/Os STR712 FR2 256+16 64 STR715 FRx 64+16 16 32 I/Os Up to 48 I/O ports - 30/32/48 multifunctional bidirectional I/Os - Up to 14 ports with interrupt capability Table 1. Device summary Features Flash - Kbytes RAM - Kbytes Peripheral Functions Operating Voltage Operating Temp. Packages T=LQFP144 20 x 20 H=LFBGA144 10 x10 STR710 FZ1 128+16 32 STR710 FZ2 256+16 64 STR710 RZ 0 64 STR711 FR0 64+16 16 STR711 FR1 128+16 32 CAN, EMI, USB, 48 I/Os USB, 30 I/Os 3.0 to 3.6V -40 to +85C T=LQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7 May 2006 Rev 8 1/74 www.st.com 74 Contents STR71xF Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Description for 144-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 EMI - Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.1 3.2 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2/74 STR71xF Contents 4 5 6 Product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Note: For detailed information on the STR710 Microcontroller memory, registers and peripherals, please refer to the STR710 Reference Manual. 3/74 Introduction STR71xF 1 Introduction This datasheet provides the STR71x Ordering Information, Mechanical and Electrical Device Characteristics. For complete information on the STR710 Microcontroller memory, registers and peripherals. please refer to the STR710 Reference Manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference Manual. 1.1 Overview ARM(R) core with embedded Flash & RAM The STR710 series is a family of ARM-powered 32-bit Microcontrollers with embedded Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have high-speed RAM but no internal Flash. The STR710 family has an embedded ARM core and is therefore compatible with all ARM tools and software. Extensive tools support STMicroelectronics' 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST's ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available. For more information, please refer to ST MCU site http://www.st.com/mcu Package Choice: Low Pin-Count 64-pin or Feature-Rich 144-pin LQFP or BGA The STR710 family is available in 5 main versions. The 144-pin versions have the full set of all features including CAN, USB and External Memory Interface (EMI). STR710F: 144-pin BGA or LQFP with CAN, USB and EMI STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash memory) 4/74 STR71xF Introduction The three 64-pin versions (BGA or LQFP) do not include External Memory Interface. STR715F: 64-pin BGA or LQFP without CAN or USB STR711F: 64-pin BGA or LQFP with USB STR712F: 64-pin BGA or LQFP with CAN High Speed Flash Memory (STR71xF) The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size, typically for the application program code. Bank 1 is 16K bytes, typically used for storing data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K write/erase cycles. Data retention is 20 years on both banks. The two banks can be accessed independently in read or write. Flash memory can be accessed in two modes: Burst mode: 64-bit wide memory access at up to 50 MHz. Direct 32-bit wide memory access for deterministic operation at up to 33 MHz. The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming. IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: Sector Write Protection Flash Debug Protection (locks JTAG access) Refer to the STR7 Flash Programming Reference manual for details. Optional External Memory (STR710) The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Figure 1 shows the general block diagram of the device family. Flexible Power Management To minimize power consumption, you can program the STR710 to switch to SLOW, WAIT, LPWAIT (low power wait), STOP or STANDBY mode depending on the current system activity in the application. Flexible Clock Control Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime. The clock to each peripheral is gated with an 5/74 Introduction STR71xF individual control bit to optimize power usage by turning off peripherals any time they are not required. Voltage Regulators The STR710 requires an external 3.0-3.6V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is switched off during low power operation. Low Voltage Detectors Each voltage regulator has an embedded LVD that monitors the internal 1.8V supply. If the regulated voltage drops below a certain threshold, the LVD will reset the STR710. This enhances the security of the system by preventing the MCU from going into an unpredictable state. An external reset circuit must be used to provide the RESET at V33 power-up. It is not sufficient to rely on the RESET generated by the LVD in this case. This is because LVD operation is guaranteed only when V33 is within the specification. 1.2 On-Chip Peripherals CAN Interface (STR710 and STR712) The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. USB Interface (STR710 and STR711) The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32 unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous transfers and USB Suspend/Resume functions. Standard Timers Each of the four timers have a 16-bit free-running counter with 7-bit prescaler Three timers each provide up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. The fourth timer is not connected to the I/O ports. It can be used by the application software for general timing functions. Realtime Clock (RTC) The RTC provides a set of continuously running counters driven by the 32 kHz external crystal. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR710 is in Standby mode the RTC can be kept running, powered by the low power voltage regulator and driven by the 32 kHz external crystal. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 1.25 Mb/s. Smart Card Interface UART1 is configurable to function either as a general purpose UART or as an asynchronous Smart Card interface as defined by ISO 7816-3. It includes Smart Card clock generation and provides support features for synchronous cards. 6/74 STR71xF Buffered Serial Peripheral Interfaces (BSPI) Introduction Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5Mb/s in Master mode and 4 Mb/s in Slave mode. I2C Interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may be used at a time. HDLC interface The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ, NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator. A/D Converter The Analog to Digital Converter, converts in single channel or up to 4 channels in singleshot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The input voltage range is 0-2.5V. Watchdog The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O Ports The 48 I/O ports are programmable as Inputs or Outputs. External Interrupts Up to 14 external interrupts are available for application use or to wake-up the application from STOP mode. 7/74 Introduction Figure 1. STR710 Block Diagram A[19:0] D[15:0] RDN WEN[1:0] STR71xF A[23:20] (AF) CS[3:0) CK CKOUT RSTIN PRCCU/PLL EXT. MEM. INTERFACE (EMI) FLASH* Program Memory 64/128/256K 16K Data FLASH* RAM 16/32/64K APB BRIDGE 1 ARM7TDMI CPU JTDI JTCK JTMS JTRST JTDO DBGRQS BOOTEN ARM7 NATIVE BUS JTAG V18[1:0] V33[6:0] VSS[9:0] V18BKP AVDD AVSS POWER SUPPLY VREG APB BRIDGE 2 I2C0 2 AF 2 AF 4 AF 4 AF 2 AF 3 AF 2 AF 2 AF 3 AF USBDP USBDN 1 AF INTERRUPT CTL(EIC) 4 AF A/D TIMER0 4 AF 2 AF 4 AF OSC 14 AF TIMER1 APB BUS I2C1 BSPI0 BSPI1 UART0 UART1 / SMARTCARD UART2 UART3 HDLC TIMER2 TIMER3 RTC APB BUS STDBY RTCXTO RTCXTI WAKEUP EXT INT (XTI) WATCHDOG USB P0[15:0] P1[15:0] P2[15:0] I/O PORT 0 I/O PORT 1 CAN I/O PORT 2 2 AF *Flash present in STR710F, not in STR710R AF: alternate function on I/O port pin 8/74 STR71xF Introduction 1.3 Related Documentation Available from www.arm.com: ARM7TDMI Technical Reference Manual Available from http://www.st.com: STR71x Reference Manual STR7 Flash Programming Reference Manual AN1774 - STR710 Software development getting started AN1775 - STR710 Hardware development getting started AN1776 - STR710 Enhanced Interrupt Controller AN1777 - STR710 Memory Mapping AN1780 - Real Time Clock with STR710 AN1781 - Four 7 Segment Display Drive Using the STR710 The above is a selected list only, a full list STR71x application notes can be viewed at http://www.st.com. 9/74 Introduction STR71xF 1.4 Pin Description for 144-Pin Packages Figure 2. STR710 LQFP Pinout P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V33 WEn.0 WEn.1 A.19 A.18 A.17 A.16 A.15 A.14 V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX A.13 A.12 A.11 A.10 A.9 A.8 A.7 A.6 A.5 V33 VSS P1.15/HTXD N.C. N.C. P0.10/U1.RX/U1.TX/SCDATA RDn P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS V33 P2.0/CSn.0 P2.1/CSn.1 P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA P2.2/CSn.2 P2.3/CSn.3 P2.4/A.20 P2.5/A.21 P2.6/A.22 BOOTEN P2.7/A.23 P2.8 N.C. N.C. VSS V33 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 JTDI JTMS JTCK JTDO JTRSTn NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 LQFP144 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 V33 VSS A.4 A.3 A.2 A.1 A.0 D.15 D.14 D.13 D.12 D.11 D.10 USBDN USBDP P1.12/CANTX P1.11/CANRX N.C. P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL D.9 D.8 D.7 D.6 D.5 P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 10/74 N.C. TEST N.C. V33IO-PLL N.C. VSSIO-PLL N.C. DBGRQS CKOUT CK P0.15/WAKEUP N.C. RTCXTI RTCXTO STDBY RSTIN N.C. VSSBKP V18BKP N.C. N.C. V18 VSS18 N.C. D.0 D.1 D.2 D.3 D.4 AVDD AVSS N.C. N.C. N.C. P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 STR71xF Table 2. A 1 2 3 4 5 6 7 8 9 10 11 12 P0.10 VSS V33 P0.6 A.19 P0.3 P0.2 A.9 VSS A.8 A.7 A.12 Introduction STR710 BGA Ball Connections B P2.0 RDn P0.9 P0.7 WEn.1 A.15 P0.1 A.10 V33 N.C. N.C. A.4 C P2.1 P0.11 P0.12 P0.8 WEn.0 A.16 P0.4 A.11 A.5 P1.15 P1.14 A.3 D VSS V33 P0.13 P0.14 P0.5 A.17 VSS18 A.13 A.6 P1.13 P1.10 P1.9 E P2.2 P2.3 P2.4 P2.5 P2.7 A.18 V18 P0.0 V33 VSS A.2 A.1 F P2.6 P2.8 N.C. N.C. VSS V33 A.14 A.0 D.15 D.14 D.13 P1.11/ CANRX G BOOT EN P2.9 P2.10 P2.11 P2.14 V18 D.12 D.11 D.10 USBDN USBDP N.C. H P2.12 JTMS JTCK JTDO N.C. N.C. D.1 P1.12/ CANTX P1.8 P1.7 VSS V33IOPLL J P2.13 JTRST n NU CK RTCXTO N.C. D.0 N.C. D.9 D.8 D.5 P1.6 K P2.15 TEST V33 CKOUT RTCXTI V18BK P nc AVSS P1.0 P1.5 P1.4 D.7 L JTDI TEST N.C. VSSIOPLL N.C. VSS BKP VSS18 D.3 N.C. P1.1 P1.3 D.6 M N.C. N.C. DBG RQS N.C. P0.15 STDBY RSTIN D.2 N.C. D.4 AVDD P1.2 Legend / Abbreviations for Table 3: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V/2V with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k weak pull-up is enabled. pd = in reset state, the internal 100k weak pull-down is enabled. OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant. Output: 11/74 Introduction Table 3. Pin n LQFP144 Type BGA144 Pin Name STR71xF STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP UART1: Receive Data input 1 A1 P0.10/U1.RX/ U1.TX/ SC.DATA I/O pd CT X 4mA T UART1: Transmit data output. Note: This pin may be used for Port 0.10 Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X External Memory Interface: Active low read signal for external memory. It maps to the OE_N input of the external components. Select Boot Port 0.11 Configuration input UART1: Transmit data output. 2 B2 RD O 5) 3 4 5 6 C2 C3 D1 D2 P0.11/BOOT.1 I/O pd /U1.TX P0.12/SC.CLK I/O pd VSS V33 S S CT CT 4mA X 4mA X X X Port 0.12 Smartcard reference clock output Ground voltage for digital I/Os4) Supply voltage for digital I/Os4) External Memory Interface: Select Memory Bank 0 output Note: This pin is forced to output push-pull 1 mode at reset to allow boot from external memory External Memory Interface: Select Memory Bank 1 output Timer2: Output Compare A output Timer2: Input Capture A input 7 B1 P2.0/CS.0 I/O 8) CT 8mA X X Port 2.0 8 C1 P2.1/CS.1 P0.13/U2.RX/ T2.OCMPA P0.14/U2.TX/ T2.ICAPA P2.2/CS.2 P2.3/CS.3 I/O pu 2) CT 8mA X X Port 2.1 9 D3 I/O pu CT X 4mA X X UART2: Port 0.13 Receive Data input UART2: Port 0.14 Transmit data output Port 2.2 Port 2.3 10 D4 I/O pu pu 2) CT 4mA X X 11 12 E1 E2 I/O I/O CT CT 8mA X 8mA X X X External Memory Interface: Select Memory Bank 3 output External Memory Interface: Select Memory Bank 4 output pu 2) 12/74 STR71xF Table 3. Pin n LQFP144 Type BGA144 Pin Name Introduction STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 E3 E4 F1 P2.4/A.20 P2.5/A.21 P2.6/A.22 I/O I/O I/O I I/O pd 3) CT CT CT CT 8mA X 8mA X 8mA X X X X PP Port 2.4 Port 2.5 Port 2.6 Boot control input. Enables sampling of BOOT[1:0] pins External Memory Interface: address bus pd 3) pd 3) G1 BOOTEN E5 F2 F3 F4 F5 F6 P2.7/A.23 P2.8 N.C. N.C. VSS V33 pd 3) CT CT 8mA X X 4mA X X X Port 2.7 Port 2.8 External Memory Interface: address bus External interrupt INT2 I/O pu Not connected (not bonded) Not connected (not bonded) S S I/O pu I/O pu I/O pu I/O pu I/O pu I/O pu I/O pu I I I O I TT CT CT CT CT CT CT CT TT TT C 8mA X X 4mA X X 4mA X X 4mA X 4mA X 4mA X 4mA X 4mA X X X X X X X X Ground voltage for digital I/Os4) Supply voltage for digital I/Os4) Port 2.9 Port 2.10 Port 2.11 Port 2.12 Port 2.13 Port 2.14 Port 2.15 JTAG Data input. External pull-up required. JTAG Mode Selection Input. External pull-up required. JTAG Clock Input. External pull-up or pull-down required. JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. Reserved, must be forced to ground. Reserved, must be forced to ground. Not connected (not bonded) Reserved, must be forced to ground. Not connected (not bonded) External interrupt INT3 External interrupt INT4 External interrupt INT5 G2 P2.9 G3 P2.10 G4 P2.11 H1 J1 P2.12 P2.13 G5 P2.14 K1 L1 H2 H3 H4 J2 J3 K2 P2.15 JTDI JTMS JTCK JTDO JTRST NU TEST M1 N.C. L2 L3 TEST N.C. 13/74 Introduction Table 3. Pin n LQFP144 Type BGA144 Pin Name STR71xF STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP X 40 41 42 43 44 45 46 47 48 49 50 K3 V33IO-PLL S Supply voltage for digital I/O circuitry and for PLL reference Not connected (not bonded) M4 N.C. L4 VSSIO-PLL S Ground voltage for digital I/O circuitry and for PLL reference4) Not connected (not bonded) M2 N.C. M3 DBGRQS K4 J4 M5 L5 K5 J5 CKOUT CK P0.15/ WAKEUP N.C. RTCXTI RTCXTO I O I I C TT X X CT 8mA Debug Mode request input (active high) Clock output (fPCLK2) Note: Enabled by CKDIS register in APB Bridge 2 Reference clock input Port 0.15 Wakeup from Standby mode input. Note: This port is input only. Not connected (not bonded) Realtime Clock input and input of 32 kHz oscillator amplifier circuit Output of 32 kHz oscillator amplifier circuit Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode. X Output: Standby mode active low output following Software Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby X Reset input Not connected (not bonded) 51 M6 STDBY I/O CT 4mA X 52 53 54 M7 RSTIN H5 L6 N.C. VSSBKP I CT S X Stabilization for low power voltage regulator. Stabilization for low power voltage regulator. Requires external capacitors of at least 1F between V18BKP and VSS18BKP. See Figure 5. X Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. Not connected (not bonded) Not connected (not bonded) 55 K6 V18BKP S 56 57 58 J6 H6 N.C. N.C. S G6 V18 Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. 14/74 STR71xF Table 3. Pin n LQFP144 Type BGA144 Pin Name Introduction STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function 59 60 61 62 63 64 65 66 67 68 69 70 71 L7 K7 J7 H7 VSS18 N.C. D.0 D.1 S PP Stabilization for main voltage regulator. Not connected (not bonded) I/O I/O I/O I/O I/O S S 6) 6) 6) 6) 6) 8mA 8mA 8mA 8mA 8mA Supply voltage for A/D Converter Ground voltage for A/D Converter Not connected (not bonded) Not connected (not bonded) Not connected (not bonded) External Memory Interface: data bus M8 D.2 L8 D.3 M10 D.4 M11 VDDA K8 J8 VSSA N.C. M9 N.C. L9 K9 N.C. P1.0/T3.OCM PB/AIN.0 I/O pu CT 4mA X X Port 1.0 Timer 3: Output Compare B ADC: Analog input 0 72 P1.1/T3.ICAP L10 A/T3.EXTCLK/ I/O pu AIN.1 P1.2/T3.OCM PA/AIN.2 P1.3/T3.ICAP B/AIN.3 P1.4/T1.ICAP A/T1.EXTCLK P1.5/T1.ICAP B P1.6/T1.OCM PB CT 4mA X X Port 1.1 Timer 3: Input Capture A or ADC: Analog input 1 External Clock input Timer 3: Output Compare A Timer 3: Input Capture B Timer 1: Input Capture A Timer 1: Input Capture B Timer 1: Output Compare B ADC: Analog input 2 73 M12 I/O pu CT 4mA X X Port 1.2 74 75 76 L11 K11 K10 I/O pu I/O pu I/O pu CT CT CT 4mA X 4mA X 4mA X X X X Port 1.3 Port 1.4 Port 1.5 ADC: Analog input 3 Timer 1: External Clock input 77 78 79 80 81 82 J12 I/O pu I/O I/O I/O I/O I/O 6) 6) 6) 6) 6) CT 4mA X 8mA 8mA 8mA 8mA 8mA X Port 1.6 J11 D.5 L12 D.6 K12 D.7 J10 D.8 J9 D.9 External Memory Interface: data bus 15/74 Introduction Table 3. Pin n LQFP144 Type BGA144 Pin Name STR71xF STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP 83 84 H12 V33IO-PLL H11 VSSIO-PLL P1.7/T1.OCM PA P1.8 S S Supply voltage for digital I/O circuitry and for PLL reference4) Ground voltage for digital I/O circuitry and for PLL reference4) CT CT 4mA X 4mA X X X Port 1.7 Port 1.8 Not connected (not bonded) CT CT X 4mA X 4mA X X X Port 1.11 Port 1.12 CAN: receive data input Note: On STR710 and STR712 only CAN: Transmit data output Note: On STR710 and STR712 only Timer 1: Output Compare A 85 86 87 88 89 H10 H9 I/O pu I/O pd G12 N.C. F12 P1.11/CANRX I/O pu H8 P1.12/CANTX I/O pu 90 G11 USBDP I/O CT USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. 8mA 8mA 8mA External Memory Interface: data bus 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA X X X X X Ground voltage for digital I/O circuitry4) Supply voltage for digital I/O circuitry4) External Memory Interface: address bus 91 92 93 94 95 96 97 98 99 G10 USBDN G9 D.10 G8 D.11 G7 D.12 F11 D.13 F10 D.14 F9 F8 D.15 A.0 I/O I/O I/O I/O I/O I/O I/O O O O O O S S I/O pd I/O pd 6) 6) 6) 6) 6) 6) 7) 7) 7) 7) 7) CT E12 A.1 100 E11 A.2 101 C12 A.3 102 B12 A.4 103 E10 VSS 104 E9 V33 105 D12 P1.9 106 D11 P1.10/ USBCLK CT C/ T 4mA X 4mA X X X Port 1.9 Port 1.10 USB: 48 MHZ clock input 16/74 STR71xF Table 3. Pin n LQFP144 Type BGA144 Pin Name Introduction STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP 107 D10 P1.13/HCLK/ I0.SCL P1.14/HRXD/ I0.SDA I/O pd CT X 4mA X X Port 1.13 HDLC: reference clock input HDLC: Receive data input I2C clock 108 C11 I/O pu CT X 4mA X X Port 1.14 I2C serial data 109 B11 N.C. 110 B10 N.C. 111 C10 P1.15/HTXD 112 113 114 115 A9 B9 C9 D9 VSS V33 A.5 A.6 I/O pu S S O O O O O O O O O 7) 7) 7) 7) 7) 7) 7) 7) 7) Not connected (not bonded) Not connected (not bonded) CT 4mA X X Port 1.15 HDLC: Transmit data output Ground voltage for digital I/O circuitry4) Supply voltage for digital I/O circuitry4) 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA X X X X X X X X X SPI0 Master in/Slave out data UART3 Transmit data output External Memory Interface: address bus 116 A11 A.7 117 A10 A.8 118 119 120 A8 B8 C8 A.9 A.10 A.11 121 A12 A.12 122 D8 A.13 123 E8 P0.0/S0.MISO I/O pu /U3.TX CT 4mA X X Port 0.0 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master UART3: Receive out/Slave in Data input data 124 B7 P0.1/S0.MOSI I/O pu /U3.RX CT X 4mA X X Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. 17/74 Introduction Table 3. Pin n LQFP144 Type BGA144 Pin Name STR71xF STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP BSPI0: Serial Clock 125 A7 P0.2/S0.SCLK I/O pu /I1.SCL CT X 4mA X X Port 0.2 I2C1: Serial clock Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data 126 A6 P0.3/S0.SS/ I1.SDA I/O pu CT 4mA X X Port 0.3 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI1: Master in/Slave out data 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 C7 D7 E7 F7 B6 C6 D6 E6 A5 B5 C5 A3 A2 D5 A4 B4 P0.4/S1.MISO I/O pu VSS18 V18 A.14 A.15 A.16 A.17 A.18 A.19 WE.1 WE.0 V33 VSS S S O O O O O O O O S S 7) 7) 7) 7) 7) 7) 5) CT 4mA X X Port 0.4 Stabilization for main voltage regulator. Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA X X X External Memory Interface: address bus X X X X X External Memory Interface: active low MSB write enable output External Memory Interface: active low LSB write enable output Supply voltage for digital I/Os4) Ground voltage for digital I/Os4) CT CT CT 4mA X X 4mA X 4mA X X X X Port 0.5 Port 0.6 Port 0.7 SPI1: Master out/Slave In data SPI1: Serial Clock SPI1: Slave Select input active low 5) P0.5/S1.MOSI I/O pu P0.6/S1.SCLK I/O pu P0.7/S1.SS I/O pu 18/74 STR71xF Table 3. Pin n LQFP144 Type BGA144 Pin Name Introduction STR710 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP Port 0.8 143 C4 P0.8/U0.RX/ U0.TX I/O pd CT X 4mA T UART0: Receive Data input UART0: Transmit data output. Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Configuration input UART0: Transmit data output 144 B3 P0.9/U0.TX/ BOOT.0 I/O pd CT 4mA X 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7 on page 28. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured by software as Alternate Function (see Table 7: Port Bit Configuration Table on page 28) to be used by the External Memory Interface. 3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address 0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7: Port Bit Configuration Table on page 28). 4. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected. 5. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Output Push-Pull. 6. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Hi-Z. 7. During the reset phase, these pins are in input pull-down state. When reset is released, they are configured as Output Push-Pull. 8. During the reset phase, and after reset is released, this pin is in Output Push-Pull state. 19/74 Introduction STR71xF 1.5 Pin description for 64-pin packages Figure 3. STR712/STR715 LQFP64 Pinout P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP64 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10 P1.9 VSS P1.12/CANTX1) P1.11/CANRX1) P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 1) CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os. 20/74 V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO STDBY RSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 STR71xF Figure 4. STR711 LQFP64 Pinout P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD Introduction P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST NU TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP64 P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 VSS USBDN USBDP P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 Table 4. A 1 2 3 4 5 6 7 8 STR711 BGA Ball Connections B P0.11 VSS P0.7 VSS P0.4 P0.1 P0.0 P1.14 C P0.12 P0.13 BOOTEN P0.8 V18 P0.3 P1.10 VSS D P0.14 VSS JTDI JTDO P0.6 P1.13 USBDN P1.8 E V33 JTMS NU AVDD P1.9 USBDP P1.7 V33IOPLL F JTCK JTRSTn STDBY V18BKP P1.0 VSSIOPLL P1.6 P1.4 G TEST P0.15 RTCXTI RSTIN V18 AVSS P1.5 P1.3 H V33IOPLL VSSIOPLL CK RTCXTO VSSBKP VSS18 P1.1 P1.2 P0.10 P0.9 P0.5 VSS18 P0.2 V33 VSS P1.15 V33IO-PLL VSSIO-PLL CK P0.15/WAKEUP RTCXTI RTCXTO STDBY RSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 21/74 Introduction Table 5. A 1 2 3 4 5 6 7 8 1) STR71xF STR712/715 BGA Ball Connections B P0.11 VSS P0.7 VSS P0.4 P0.1 P0.0 P1.14 C P0.12 P0.13 BOOTEN P0.8 V18 P0.3 P1.10 VSS D P0.14 VSS JTDI JTDO P0.6 P1.13 P1.12/ CANTX1) P1.8 E V33 JTMS NU AVDD P1.9 P1.11/ CANRX1) P1.7 V33IOPLL F JTCK JTRSTn STDBY V18BKP P1.0 VSSIOPLL P1.6 P1.4 G TEST P0.15 RTCXTI RSTIN V18 AVSS P1.5 P1.3 H V33IOPLL VSSIOPLL CK RTCXTO VSSBKP VSS18 P1.1 P1.2 P0.10 P0.9 P0.5 VSS18 P0.2 V33 VSS P1.15 CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os. Legend / Abbreviations for Table 6: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.8V / 2V with input trigger TT= TTL 0.3V/0.7VDD with input trigger C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V Port and control configuration: Input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k weak pull-up is enabled. pd = in reset state, the internal 100k weak pull-down is enabled. OD = open drain (logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to VDD not implemented), Output: 5V tolerant. 22/74 STR71xF Table 6. Pin n Type LQFP64 BGA64 Pin Name Introduction STR711/STR712/STR715 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP UART1: Receive Data input 1 P0.10/U1.RX/ A1 U1.TX/ SC.DATA I/O pd CT X 4mA T UART1: Transmit data output. Note: This pin may be used for Port 0.10 Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Select Boot Port 0.11 Configuration input UART1: Transmit data output. 2 3 4 5 B1 P0.11/BOOT.1 I/O pd /U1.TX CT CT 4mA 4mA X C1 P0.12/SC.CLK I/O pd B2 VSS C2 P0.13/U2.RX/ T2.OCMPA P0.14/U2.TX/ T2.ICAPA S I/O pu Port 0.12 Smartcard reference clock output Ground voltage for digital I/Os2) CT X 4mA X X UART2: Port 0.13 Receive Data input UART2: Port 0.14 Transmit data output Timer2: Output Compare A output Timer2: Input Capture A input 6 D1 I/O pu CT 4mA X X 7 8 9 C3 BOOTEN D2 VSS E1 V33 I S S I I I O I CT Boot control input. Enables sampling of BOOT[1:0] pins Ground voltage for digital I/Os2) Supply voltage for digital I/Os2) 10 D3 JTDI 11 E2 JTMS 12 F1 JTCK 13 D4 JTDO 14 F2 JTRST 15 E3 NU 16 G1 TEST 17 H1 V33IO-PLL 18 H2 VSSIO-PLL 19 H3 CK TT TT C 8mA TT X JTAG Data input. External pull-up required. JTAG Mode Selection Input. External pull-up required. JTAG Clock Input. External pull-up or pull-down required. JTAG Data output. Note: Reset state = HiZ. JTAG Reset Input. External pull-up required. Reserved, must be forced to ground. Reserved, must be forced to ground. S S I C Supply voltage for digital I/O circuitry and for PLL reference2) Ground voltage for digital I/O circuitry and for PLL reference2) Reference clock input 23/74 Introduction Table 6. Pin n Type LQFP64 BGA64 Pin Name STR71xF STR711/STR712/STR715 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP 20 G2 P0.15/ WAKEUP Port 0.15 Wakeup from Standby mode input. I TT X X Note: This port is input only. Realtime Clock input and input of 32 kHz oscillator amplifier circuit Output of 32 kHz oscillator amplifier circuit Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode. X Output: Standby mode active low output following Software Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby. X Reset input X Stabilization for low power voltage regulator. Stabilization for low power voltage regulator. Requires external capacitors of at least 1F between V18BKP and VSS18BKP. See Figure 5. X Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. Stabilization for main voltage regulator. Supply voltage for A/D Converter Ground voltage for A/D Converter CT 4mA X X Port 1.0 Timer 3: Output ADC: Analog input 0 Compare B Timer 3: Input Capture A or External Clock input 21 G3 RTCXTI 22 H4 RTCXTO 23 F3 STDBY I/O CT 4mA X 24 G4 RSTIN 25 H5 VSSBKP I CT S 26 F4 V18BKP S 27 G5 V18 28 H6 VSS18 29 E4 VDDA 30 G6 VSSA 31 F5 P1.0/T3.OCM PB/AIN.0 S S S S I/O pu P1.1/T3.ICAP 32 H7 A/T3.EXTCLK I/O pu /AIN.1 33 H8 34 G8 35 F8 P1.2/T3.OCM PA/AIN.2 P1.3/T3.ICAP B/AIN.3 I/O pu I/O pu CT 4mA X X Port 1.1 ADC: Analog input 1 CT CT CT 4mA 4mA 4mA X X X X X X Port 1.2 Port 1.3 Port 1.4 Timer 3: Output ADC: Analog input 2 Compare A Timer 3: Input Capture B Timer 1: Input Capture A ADC: Analog input 3 Timer 1: External Clock input P1.4/T1.ICAP I/O pu A/T1.EXTCLK 24/74 STR71xF Table 6. Pin n Type LQFP64 BGA64 Pin Name Introduction STR711/STR712/STR715 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function 36 G7 37 F7 P1.5/T1.ICAP B P1.6/T1.OCM PB PP I/O pu I/O pu S S I/O pu I/O pd CT CT 4mA 4mA X X X X Port 1.5 Port 1.6 Timer 1: Input Capture B Timer 1: Output Compare B 38 E8 V33IO-PLL 39 F6 VSSIO-PLL 40 E7 P1.7/T1.OCM PA Supply voltage for digital I/O circuitry and for PLL reference2) Ground voltage for digital I/O circuitry and for PLL reference2) CT CT CT CT 4mA 4mA X 4mA 4mA X X X X X X X X Port 1.7 Port 1.8 Port 1.11 Port 1.12 CAN: receive data input Note: On STR710 and STR712 only CAN: Transmit data output Note: On STR710 and STR712 only Timer 1: Output Compare A 41 D8 P1.8 42 E6 P1.11/CANRX I/O pu 43 D7 P1.12/CANTX I/O pu 42 E6 USBDP I/O CT USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V33 to maintain a high level. USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only. Ground voltage for digital I/O circuitry2) 43 D7 USBDN 44 C8 VSS 45 E5 P1.9 46 C7 P1.10/USBCL K P1.13/HCLK/I 0.SCL I/O S I/O pd I/O pd CT CT C/ T CT 4mA 4mA X X X X Port 1.9 Port 1.10 USB: 48 MHZ clock input 47 D6 I/O pd X 4mA X X HDLC: Port 1.13 reference clock I2C clock input Port 1.14 HDLC: Receive I2C serial data data input 48 B8 P1.14/HRXD/I I/O pu 0.SDA I/O pu S S CT CT X 4mA 4mA X X X X 49 A8 P1.15/HTXD 50 A7 VSS 51 A6 V33 Port 1.15 HDLC: Transmit data output Ground voltage for digital I/O circuitry2) Supply voltage for digital I/O circuitry2) 25/74 Introduction Table 6. Pin n Type LQFP64 BGA64 Pin Name STR71xF STR711/STR712/STR715 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP SPI0 Master in/Slave out data 52 B7 P0.0/S0.MISO I/O pu /U3.TX CT 4mA X X Port 0.0 UART3 Transmit data output Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Master out/Slave in data UART3: Receive Data input 53 B6 P0.1/S0.MOSI I/O pu /U3.RX CT X 4mA X X Port 0.1 Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. BSPI0: Serial Clock I2C1: Serial clock 54 A5 P0.2/S0.SCLK I/O pu /I1.SCL CT X 4mA X X Port 0.2 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. SPI0: Slave Select input active low. I2C1: Serial Data 55 C6 P0.3/S0.SS/I1 I/O pu .SDA CT 4mA X X Port 0.3 Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register. 56 B5 P0.4/S1.MISO I/O pu 57 A4 VSS18 58 C5 V18 59 B4 VSS S S S CT 4mA X X Port 0.4 SPI1: Master in/Slave out data Stabilization for main voltage regulator. Stabilization for main voltage regulator. Requires external capacitors of at least 10F + 33nF between V18 and VSS18. See Figure 5. Ground voltage for digital I/Os CT CT CT 4mA X 4mA 4mA X X X X X X Port 0.5 Port 0.6 Port 0.7 SPI1: Master out/Slave In data SPI1: Serial Clock SPI1: Slave Select input active low 60 A3 P0.5/S1.MOSI I/O pu 61 D5 P0.6/S1.SCLK I/O pu 62 B3 P0.7/S1.SS I/O pu 26/74 STR71xF Table 6. Pin n Type LQFP64 BGA64 Pin Name Introduction STR711/STR712/STR715 Pin Description Reset State1) Input Input Level interrupt Output Capability Active in Stdby Main function (after reset) OD Alternate function PP Port 0.8 63 C4 P0.8/U0.RX/U I/O pd 0.TX CT X 4mA T UART0: Receive Data input UART0: Transmit data output. Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress X Port 0.9 Select Boot Configuration input UART0: Transmit data output 64 A2 P0.9/U0.TX/B OOT.0 I/O pd CT 4mA X 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7 on page 28. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected. 1.6 External Connections Figure 5. Recommended External Connection of V18 and V18BKP pins 33 nF 129 128 V18 33 nF 58 57 V18 LQFP144 V18BKP V18 LQFP64 V18BKP V18 54 55 58 59 1F 10 F 25 26 27 28 1F 10 F 27/74 Introduction STR71xF 1.7 Table 7. I/O Port Configuration Port Bit Configuration Table PxD Configuration Mode Input Buffer Register Read access I/O pin I/O pin I/O pin I/O pin 0 I/O pin last value written I/O pin I/O pin Write access don't care don't care 0 1 don't care 0 or 1 0 or 1 don't care don't care PxC2 PxC1 PxC0 Register Register Register TTL Input Floating CMOS Input Floating CMOS Input Pull-Down (IPUPD) CMOS Input Pull-Up (IPUPD) Analog input Output Open-Drain Output Push-Pull OUTPUT TTL floating CMOS floating CMOS PullDown CMOS Pull-Up AIN N.A. N.A. 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 1 0 1 INPUT Alternate Function Open-Drain CMOS floating Alternate Function Push-Pull Legend: AIN: Analog Input CMOS: CMOS Input levels IPUPD: Input Pull Up /Pull Down TTL: TTL Input levels CMOS floating N.A.: not applicable. In Output mode, a read access to the port gets the output latch value. 28/74 STR71xF Introduction 1.8 Memory Mapping Figure 6. Memory Map APB Memory Space 0xFFFF FFFF Addressable Memory Space 4 Gbytes 0xFFFF FFFF 0xFFFF F800 EIC 0xFFFF F800 0xE000 E000 0xE000 D000 0xE000 C000 EIC WDG RTC TIMER 3 TIMER 2 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 7 0xE000 B000 APB2 0xE000 0000 64K TIMER 1 0xE000 A000 TIMER 0 0xE000 9000 0xE000 8000 CLKOUT ADC reserved IOPORT 2 IOPORT 1 IOPORT 0 6 0xE000 7000 APB1 0xC000 0000 64K FLASH Memory Space 272 Kbytes + regs 0x4010 DFBF FLASH Registers 0x4010 0000 0xE000 6000 0xE000 5000 0xE000 4000 0xE000 3000 5 0xA000 0000 PRCCU 36b 1K 0x400C 4000 reserved reserved 0xE000 2000 0xE000 1000 XTI APB BRIDGE 2 REGS B1F1 8K 0xE000 0000 4 0x8000 0000 Reserved 0x400C 2000 B1F0 8K 0xC001 0000 reserved 4K 0x400C 0000 reserved 0xC000 F000 0xC000 E000 0xC000 D000 reserved HDLC + RAM reserved reserved BSPI 1 BSPI 0 CAN USB + RAM UART 3 UART 2 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 3 EXTMEM 0x4004 0000 See Figure 8 0x6000 0000 64MB B0F7 64K 0xC000 C000 0xC000 B000 0x4003 0000 2 B0F6 0x4000 0000 FLASH 0xC000 A000 0xC000 9000 0xC000 8000 0x4002 0000 0xC000 7000 0xC000 6000 B0F5 64K 256K+16K+36b 1 64K 0x2000 0000 RAM 0xC000 5000 0xC000 4000 UART 1 UART 0 reserved 64K 0x4001 0000 0xC000 3000 B0F4 32K 0xC000 2000 I2C 1 I C0 APB BRIDGE 1 REGS 2 0 0x0000 0000 FLASH/RAM/EMI 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F3 B0F2 B0F1 B0F0 8K 8K 8K 8K 0xC000 1000 0xC000 0000 (*) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes) Reserved 29/74 Introduction Figure 7. Mapping of Flash Memory Versions FLASH Memory Space 128 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Registers 0x4010 0000 reserved 0x400C 4000 B1F1 0x400C 2000 B1F0 0x400C 0000 reserved 0x4004 0000 0x4004 0000 0x400C 4000 FLASH Registers 0x4010 0000 reserved 0x400C 4000 B1F1 0x400C 2000 STR71xF FLASH Memory Space 64 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Memory Space 256 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Registers 0x4010 0000 reserved 36b 36b 36b 8K 8K 0x400C 2000 B1F1 8K 8K 0x400C 0000 B1F0 8K 0x400C 0000 B1F0 8K reserved 0x4004 0000 reserved reserved 64K reserved 64K B0F7 64K 0x4003 0000 0x4003 0000 0x4003 0000 reserved 64K reserved 64K B0F6 64K 0x4002 0000 0x4002 0000 0x4002 0000 reserved 64K 0x4001 0000 B0F5 64K 0x4001 0000 B0F5 64K 0x4001 0000 B0F4 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F3 B0F2 B0F1 B0F0 32K 8K 8K 8K 8K 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F4 B0F3 B0F2 B0F1 B0F0 32K 8K 8K 8K 8K 0x4000 0x4000 0x4000 0x4000 0x4000 8000 6000 4000 2000 0000 B0F4 B0F3 B0F2 B0F1 B0F0 32K 8K 8K 8K 8K STR715FR0xx STR711FR0xx STR712FR0xx STR710FZ1xx STR711FR1xx STR712FR1xx STR710F72xx STR711FR2xx STR712FR2xx Table 8. RAM Memory Mapping RAM Size Start Address End Address Part Number STR715FR0xx STR711FR0xx STR712FR0xx STR710FZ1xx STR711FR1xx STR712FR1xx STR710FR2xx STR710Rxx STR711FR2xx STR712FR2xx 16 Kbytes 0x2000 0000 0x2000 3FFF 32 Kbytes 0x2000 0000 0x2000 7FFF 64 Kbytes 0x2000 0000 0x2000 FFFF 30/74 STR71xF Figure 8. External Memory Map Addressable Memory Space 4 Gbytes 0xFFFF FFFF 0xFFFF F800 EIC Introduction 7 0xE000 0000 APB2 6 0xC000 0000 APB1 External Memory Space 64 MBytes 5 0xA000 0000 PRCCU 0x6C00 0x6C00 0x6C00 0x6C00 000C 0008 0004 0000 BCON3 BCON2 BCON1 BCON0 register register register register 4 0x66FF FFFF 0x8000 0000 Reserved Bank3 CSn.3 16M 3 0x6000 0000 EXTMEM 0x6600 0000 0x64FF FFFF Bank2 CSn.2 16M 0x6400 0000 2 0x4000 0000 FLASH 0x62FF FFFF Bank1 CSn.1 16M 0x6200 0000 0x60FF FFFF 1 CSn.0 0x2000 0000 RAM Bank0 16M 0x6000 0000 0 0x0000 0000 FLASH/RAM/EMI Reserved Drawing not in scale 31/74 Electrical parameters STR71xF 2 2.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 2.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 2.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, V33=3.3V (for the 3.0VV333.6V voltage range) and V18=1.8V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 2.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 2.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 2.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage STR7 PIN STR7 PIN L=50pF VIN 32/74 STR71xF Electrical parameters 2.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Voltage characteristics Ratings External 3.3V Supply voltage (including AVDD and V33IOPLL) 2) Symbol Min Max Unit V33- VSS -0.3 4.0 V18BKP - VSSBKP Digital 1.8V Supply voltage on V18BKP backup supply 2) Input voltage on true open drain pin (P0.10) 1) Input voltage on any other pin 1) Variations between different 3.3V power pins Variations between different 1.8V power pins 5) Variations between all the different ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) -0.3 2.0 V VSS-0.3 VSS-0.3 50 25 50 +5.5 V33+0.3 50 25 50 mV VIN |V33x| |V18x| |VSSX - VSS| VESD(HBM) VESD(MM) see : Absolute Maximum Ratings (Electrical Sensitivity) on page 47 33/74 Electrical parameters Table 10. Symbol IV33 IVSS IIO STR71xF Current characteristics Ratings Total current into V33/V33IO-PLL power lines (source) 2) Total current out of VSS/VSSIO-PLL ground lines (sink) 2) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on RSTIN pin Max. 150 150 25 - 25 5 5 5 25 mA Unit IINJ(PIN) 1) & 3) Injected current on CK pin Injected current on any other pin 4) IINJ(PIN) 1) Notes: Total injected current (sum of all I/O and control pins) 4) 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>V33 while a negative injection is induced by VIN Thermal characteristics Ratings Storage temperature range Value -65 to +150 Unit C Symbol TSTG TJ Maximum junction temperature (see Section 3.2: Thermal characteristics on page 69) 34/74 STR71xF Electrical parameters 2.3 Operating conditions Subject to general operating conditions for V33, and TA. Table 12. Symbol General Operating Conditions Parameter Conditions Accessing SRAM or external memory with 0 wait states Accessing FLASH in burst mode Executing from FLASH with RWW Accessing FLASH with 0 wait states Min 0 0 0 0 0 3.0 1.4 -40 Max 66 50 MHz 45 1) 33 33 3.6 1.8 85 MHz V V C Unit fMCLK Internal CPU Clock frequency fPCLK V33 V18BKP TA Internal APB Clock frequency Standard Operating Voltage (includes V33I0_PLL) Backup Operating Voltage Ambient temperature range 6 Partnumber Suffix 1. Data guaranteed by characterization, not tested in production Table 13. Symbol Operating Conditions at power-up / power-down Parameter V33 rise time rate Conditions Subject to general operating conditions for TA. Min 20 20 Typ Max Unit s/V ms/V tV33 35/74 Electrical parameters STR71xF 2.3.1 Supply current characteristics The current consumption is measured as described in Figure 9 on page 32 and Figure 10 on page 32. Total current consumption The MCU is placed under the following conditions: All I/O pins in input mode with a static value at V33 or VSS (no load) All peripherals are disabled except if explicitly mentioned. Embedded Regulators are used to provide 1.8V (except if explicitly mentioned) Subject to general operating conditions for V33, and TA. Table 14. Symbol Total Current consumption Parameter Supply current in RUN mode Conditions fMCLK=66 MHz, RAM execution fMCLK=32 MHz, Flash non-burst execution TA=25C OSC32K bypassed Typ 1) Max 2) 73.6 49.3 10 12 503) 30 A A 100 mA Unit IDD4) Supply current in STOP mode Supply current in STANDBY mode Notes: 1. Typical data are based on TA=25C, V33=3.3V. 2. Data based on characterization results, tested in production at V33, fMCLK max. and TA max. 3. Based on device characterisation, device power consumption in STOP mode at TA 25C is predicted to be 30A or less in 99.730020% of parts. 4. The conditions for these consumption measurements are described in application note AN2100. 36/74 STR71xF Table 15. Symbol Electrical parameters Typical power consumption data Parameter Conditions MCLK = 16 MHz, PCLK = FCLK = 16 MHz MCLK = 32 MHz, PCLK = FCLK = 32 MHz All periphs ON MCLK = 48 MHz, PCLK = FCLK = 24 MHz RUN mode current from RAM All periphs OFF MCLK = 48 MHz 39 48 27 47 62 21 36 53 1.7 13 37 18 10 10 9 5 1 A mA MCLK = 64 MHz, PCLK = FCLK = 32 MHz MCLK = 16 MHz MCLK = 32 MHz 50 63 16 26 Typical current on V33 23 40 Unit IDDRUN MCLK = 64 MHz MCLK = 16 MHz, PCLK = FCLK = 16 MHz All periphs ON RUN mode current from FLASH MCLK = 32 MHz, PCLK = FCLK = 32 MHz MCLK = 48 MHz, PCLK = FCLK = 24 MHz MCLK = 16 MHz All periphs OFF MCLK = 32 MHz MCLK = 48 MHz IDDSLOW IDDWAIT IDDLPWAIT SLOW mode current WAIT mode current (all periphs ON) LPWAIT mode current MCLK = CK_AF (32 kHz), MVR off PCLK = FCLK = 1 MHz CK_AF (32 kHz), Main VReg off, FLASH in power-down Main VReg off, FLASH in power down, RTC on IDDSTOP STOP mode current Main VReg off, FLASH in power down, RTC off LP VReg on, LVD on, RTC on LP VReg off (ext 1.8V on V18BKP), LVD on, RTC on IDDSB STANDBY mode current LP VReg off (ext1.8V on V18BKP), LVD off, RTC on LP VReg off (ext 1.8V on V18BKP), LVD off, RTC off 37/74 Electrical parameters STR71xF Figure 11. STOP IDD vs. V33 100 90 80 70 Figure 12. STANDBY IDD vs. V33 25 TA=-45 to +25C TA=+90C 20 TA=-45C TA=0C TA=+25C TA=+90C IDDSTDBY (A) 3 3.1 3.2 3.3 3.4 3.5 3.6 IDDSTOP (A) 15 60 50 40 30 20 10 0 10 5 0 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) V33 (V) Figure 13. WFI IDD vs. V33 100 90 IDDWFI (A) 80 70 TA=-40 to +90C 60 50 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) 38/74 STR71xF Electrical parameters On-Chip Peripherals Table 16. Symbol Peripheral current consumption Parameter Conditions Typ 3.42 5.81 0.88 1.1 1.05 mA Unit IDD(PLL1) PLL1 supply current IDD(PLL2) PLL2 supply current IDD(TIM) TIM Timer supply current 1) TA= 25C IDD(BSPI) BSPI supply current 2) IDD(UART) UART supply current 2) IDD(I2C) IDD(ADC) I2C supply current 2) ADC supply current when converting 5) TA= 25C, fPCLK=33 MHz 0.45 1.89 1.82 2.08 1.11 IDD(HDLC) HDLC supply current 2) IDD(USB) IDD(CAN) Notes: USB supply current 2) CAN supply current 2) 1. Data based on a differential IDD measurement between reset configuration and timer counter running at 16MHz. No IC/OC programmed (no I/O pads toggling). 2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. 39/74 Electrical parameters STR71xF 2.3.2 Clock and timing characteristics External Clock Sources Subject to general operating conditions for V33, and TA. Table 17. Symbol fCK VCKH VCKL tw(CK) tw(CK) tr(CK) tf(CK) IL Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. CK External Clock Characteristics Parameter External clock source frequency CK input pin high level voltage CK input pin low level voltage CK high or low time 1) time 1) VSSVINV33 Conditions Min 0 0.7xV33 VSS 25 ns CK rise or fall 5 1 A Typ Max 16.5 V33 V 0.3xV33 Unit MHz CK Input leakage current Figure 14. CK External Clock Source 90% VCKH 10% VCKL tr(CK) tf(CK) tw(CKH) tw(CKL) TCK fCLK EXTERNAL CLOCK SOURCE CK IL STR710 40/74 STR71xF Table 18. Symbol fRTCXT1 VRTCXT1H VRTCXT1L Electrical parameters RTCXT1 External Clock Characteristics Parameter External clock source frequency RTCXT1 input pin high level voltage RTCXT1 input pin low level voltage Conditions Min 0 0.7xV33 VSS 100 ns 5 VSSVINV33 1 A Typ Max 500 V33 V 0.3xV33 Unit kHz tw(RTCXT1) 1) tw(RTCXT1) RTCXT1 high or low time tr(RTCXT1) 1) tf(RTCXT1) RTCXT1 rise or fall time IL Notes: RTCXT1 Input leakage current 1. Data based on design simulation and/or technology characteristics, not tested in production. 41/74 Electrical parameters STR71xF OSC32K Crystal / Ceramic Resonator Oscillator The STR7 RTC clock can be supplied with a 32kHz Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 19. Symbol RF CL1 CL2 i2 gm 32K Oscillator characteristics (fOSC32K= 32.768kHz) Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)1) RTCXT2 driving current Oscillator Transconductance V33 is stabilized RS=40K V33=3.3V VIN=VSS Conditions Typ 2.7 12.5 Unit M pF 3.2 8 3 A A/V s tSU(OSC32KHZ)2) startup time Notes: 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 2. tSU(OSC32KHZ) is the start-up time measured from the moment it is enabled (by software) to a stabilized 32kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 15. Typical Application with a 32kHz Crystal WHEN RESONATOR WITH INTEGRATED CAPACITORS i2 FEEDBACK LOOP CL1 RTCXT1 fOSC32K CL2 32KHz RESONATOR RTCXT2 RF STR710 42/74 STR71xF Figure 16. RTC Crystal Oscillator and Resonator Electrical parameters RTCXTO RS CL CL PLL Electrical Characteristics V33 = 3.0 to 3.6V, V33IOPLL = 3.0 to 3.6V, TA = -40 / 85 C unless otherwise specified. Table 20. Symbol PLL1 Characteristics Value Parameter Test Conditions Min Typ Max 165 1.5 3.0 3.0 8.25 MHz MHz MHz fPLL1x 24 FREF_RANGE = 0 FREF_RANGE = 1 PLL input clock MX[1:0]='00' or `01' FREF_RANGE = 1 MX[1:0]='10' or `11' PLL input clock duty cycle FREF_RANGE = 0 MX[1:0]='01' or `11' FREF_RANGE = 0 MX[1:0]='00' or `10' Unit fPLLCLK1 PLL multiplier output clock fPLL1 3.0 25 125 RTCXTO RTCXTI RTCXTI DEVICE DEVICE 6 75 MHz % kHz 250 kHz fFREE1 PLL free running frequency FREF_RANGE = 1 MX[1:0]='01' or `11' FREF_RANGE = 1 MX[1:0]='00' or `10' FREF_RANGE = 0 Stable Input Clock 250 kHz 500 kHz 300 s tLOCK1 PLL lock time Stable V33IOPLL, V18 FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 s tJITTER1 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]='11' Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns 43/74 Electrical parameters Table 21. Symbol STR71xF PLL2 Characteristics Value Parameter PLL multiplier output clock PLL input clock FREF_RANGE = 1 FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]='11' Global Output division = 32 (Output Clock = 2 MHz) 0.7 3.0 5 300 MHz s Test Conditions Min Typ Max 140 1.5 3.0 MHz MHz Unit fPLLCLK2 fPLL2 fPLL x 28 FREF_RANGE = 0 tLOCK2 PLL lock time 600 s tJITTER2 2 ns Table 22. Symbol tWULPWFI tWUSTOP tWUSTBY Low-power Mode Wake-up Timing Parameter Wake-up from LPWFI mode Wake-up from STOP mode Wake-up from STANDBY mode Typ 26 131 2 Unit s s s 44/74 STR71xF Electrical parameters 2.3.3 Memory characteristics Flash Memory V33 = 3.0 to 3.6V, TA = -40 to 85 C unless otherwise specified. Table 23. Symbol tPW tPDW tPB0 tPB1 tES tES tES tES tRPD2) tPSL2) tESL2) NEND_B0 NEND_B1 tRET Flash memory characteristics Value Parameter Word Program Double Word Program Bank 0 Program (256K) Bank 1 Program (16K) Sector Erase (64K) Double Word Program Double Word Program Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Test Conditions Min. Typ 40 60 1.6 130 2.3 1.9 0.7 0.6 8.0 6.6 0.9 0.8 2.1 170 4.0 3.3 1.1 1.0 13.7 11.2 1.5 1.3 20 10 300 10 100 TA=55 Min time from Erase Resume to next Erase Suspend 20 Max1) s s s ms s Unit Sector Erase (8K) s Bank 0 Erase (256K) s Bank 1 Erase (16K) Recovery when disabled Program Suspend Latency Erase Suspend Latency Endurance (Bank 0 sectors) Endurance (Bank 1 sectors) Data Retention (Bank 0 and Bank 1) Erase Suspend Rate s s s s kcycles kcycles Years tESR 20 ms Notes: 1. TA=85C after 0 cycles. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production 2.3.4 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 45/74 Electrical parameters STR71xF Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). In the case of an ARM7 CPU, in order to write robust code that can withstand all kinds of stress, such as very strong electromagnetic disturbance, it is mandatory that the Data Abort, Prefetch Abort and Undefined Instruction exceptions are managed by the application software. This will prevent the code going into an undefined state or performing any unexpected operation. 46/74 STR71xF Table 24. Symbol VFESD Electrical parameters EMS data Parameter Conditions Level/ Class 2B Voltage limits to be applied on any I/O pin to V33=3.3V, TA=+25C, fMCLK=32MHz induce a functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be V33=3.3V, TA=+25C, fMCLK=32MHz applied through 100pF on VDD and VSS pins conforms to IEC 1000-4-4 to induce a functional disturbance VEFTB 4A Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 25. EMI data Max vs. [fOSC4M/fHCLK] Unit 16/ 48MHz 17 17 11 4 16/8MHz 19 16 11 3 dBV Symbol Parameter Conditions Monitored Frequency Band SEMI Peak level 0.1MHz to 30 MHz V33=3.3V, TA=+25C, 30 MHz to 130 MHz LQFP64 package conforming to SAE J 130 MHz to 1GHz 1752/3 SAE EMI Level Notes: 1. Not tested in production. 2. BGA and LQFP devices have similar EMI characteristics. Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. 47/74 Electrical parameters Table 26. Symbol VESD(HBM) VESD(MM) STR71xF ESD Absolute Maximum ratings Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Electro-static discharge voltage (Charge Device Model) TA=+25C Conditions Maximum value 1) 2000 200 750 on corner pins, 500 on others Unit V VESD(CDM) Notes: 1. Data based on characterization results, not tested in production. Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical Sensitivities Symbol LU Parameter Static latch-up class TA=+25C TA=+85C TA=+105C VDD=3.3V, fOSC4M=4MHz, fMCLK=32MHz, TA=+25C Conditions Class 1) A A A A DLU Dynamic latch-up class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 48/74 STR71xF Electrical parameters 2.3.5 I/O port pin characteristics General Characteristics Subject to general operating conditions for V33 and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 27. Symbol VIL VIH Vhys VIL VIH Vhys VIL VIH IINJ(PIN) I/O static characteristics Parameter Input low level voltage 1) Input high level voltage 1) Schmitt trigger voltage hysteresis 2) Conditions Min Typ Max 0.3V33 Unit V CMOS ports 0.7V33 0.8 0.9 P0.15 WAKEUP 2 1.35 0.4 0.8 TTL ports Input high level voltage 1) Injected Current on any I/O pin 2.0 4 mA 25 VSSVINV33 VIN=VSS VIN=V33 110 110 150 150 5 1 700 700 A k k pF V V 0.8 V Input high level voltage 1) Schmitt trigger voltage hysteresis 2) V Input low level voltage 1) Input low level voltage 1) IINJ(PIN) Total injected current (sum of all 3) I/O and control pins) Ilkg RPU RPD CIO Notes: 1. Data based on characterization results, not tested in production. Input leakage current 4) Weak pull-up equivalent resistor5) Weak pull-down equivalent resistor5) I/O pin capacitance 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 3. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>V33 while a negative injection is induced by VIN Electrical parameters STR71xF Figure 17. RPU vs. V33 with VIN=VSS 0.0 Figure 18. IPU vs. V33 with VIN=VSS 0 -50.0 TA=-45C TA=0C TA=+25C TA=+90C -5 TA=-45C TA=0C TA=+25C TA=+90C -10 RPU (kohm) IPU (A) -100.0 -15 -150.0 -20 -200.0 -25 -250.0 3 3.1 3.2 3.3 3.4 3.5 3.6 -30 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) V33 (V) Figure 19. RPD vs. V33 with VIN=V33 300.0 Figure 20. IPD vs. V33 with VIN=V33 30 250.0 TA=-45C TA=0C TA=+25C TA=+90C 25 TA=-45C TA=0C TA=+25C TA=+90C 200.0 RPD (kohm) 20 150.0 IPD (A) 3 3.1 3.2 3.3 3.4 3.5 3.6 15 100.0 10 50.0 5 0.0 0 3 3.1 3.2 3.3 3.4 3.5 3.6 V33 (V) V33 (V) 50/74 STR71xF Electrical parameters Output Driving Current Subject to general operating conditions for V33 and TA unless otherwise specified. Table 28. Output driving current Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time (see Figure 21) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 21 and Figure 23) Output low level voltage for an I/O pin when 8 pins are sunk at same time (see Figure 21) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 21 and Figure 23) Conditions Min Max Unit I/O Symbol Type VOL 1) Standard IIO=+4mA 0.4 VOH 2) IIO=-4mA V33-0.8 V High Current VOL 1) IIO=+8mA 0.4 VOH 2) IIO=-8mA V33-0.8 Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 10 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 10 and the sum of IIO (I/O ports and control pins) must not exceed IV33. 51/74 Electrical parameters Figure 21. Typical VOL and VOH at V33=3.3V (High current ports) 3.09 3.08 3.07 3.06 0.16 STR71xF TA=-45C TA=0C TA=+25C TA=+90C 0.14 0.12 0.10 VOH(V) 3.05 3.04 3.03 3.02 3.01 -4 -8 VOL(V) 0.08 0.06 0.04 0.02 0.00 -4 TA=-45C TA=0C TA=+25C TA=+90C -8 Iio(mA) Iol (mA) 52/74 STR71xF Figure 22. Typical VOL vs. V33 0.16 0.14 0.12 0.18 0.16 0.14 Electrical parameters VOL (V) Iio=4mA 0.10 0.08 0.06 0.04 0.02 0.00 3 3.1 3.2 3.3 3.4 3.5 3.6 VOL(V) Iio=8mA 0.12 0.10 0.08 0.06 0.04 0.02 0.00 3 3.1 3.2 3.3 3.4 3.5 3.6 TA=-45C TA=0C TA=+25C TA=+90C TA=-45C TA=0C TA=+25C TA=+90C V33 (V) V33 (V) Figure 23. Typical VOH vs. V33 3.60 3.40 3.20 3.60 3.40 3.20 VOH (V) Iio=4mA VOH(V) Iio=8mA 3.00 2.80 2.60 2.40 2.20 2.00 3 3.1 3.2 3.3 3.4 3.5 3.6 3.00 2.80 2.60 2.40 2.20 2.00 3 3.1 3.2 3.3 3.4 3.5 3.6 TA=-45C TA=0C TA=+25C TA=+90C TA=-45C TA=0C TA=+25C TA=+90C V33 (V) V33 (V) 53/74 Electrical parameters STR71xF RSTIN Pin The RSTIN pin input driver is CMOS. A permanent pull-up is present which is the same as as RPU (seeTable 27 on page 49) Subject to general operating conditions for V33 and TA unless otherwise specified. Table 29. Symbol RESET pin characteristics Parameter Conditions Min Typ 1) Max 0.8 V 2 500 1.2 ns s Unit VIL(RSTINn) RSTIN Input low level voltage 1) VIH(RSTINn) RSTIN Input high level voltage 1) VF(RSTINn) RSTIN Input filtered pulse2) VNF(RSTINn) RSTIN Input not filtered pulse2) Notes: 1. Data based on characterization results, not tested in production. 2) Data guaranteed by design, not tested in production. Figure 24. Recommended RSTIN pin protection.1) Recommended V33 V33 V33 0.01F EXTERNAL RESET CIRCUIT 0.01F 4.7k RSTIN RPU Filter INTERNAL RESET STR7X Required Notes: 1. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 18). 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the RSTIN pin can go below the VIL(RSTINn) max. level specified in Table 29. Otherwise the reset will not be taken into account internally. 2.3.6 TIM timer characteristics Subject to general operating conditions for V33, fMCLK, and TA unless otherwise specified. Refer to Section 2.3.5: I/O port pin characteristics on page 49 for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 30. Symbol tw(ICAP)in TIM characteristics Parameter Input capture pulse time Conditions Min 2 Typ Max Unit tCK_TIM 54/74 STR71xF Table 30. Symbol tres(TIM) Electrical parameters TIM characteristics Parameter Timer resolution time fPCLK2 = 30MHz fCK_TIM(MAX) = fMCLK fCK_TIM = fMCLK = 60MHz 33.3 0 0 fCK_TIM/4 15 16 1 fPCLK2 = 30MHz 0.033 65536 2184 65536x 65536 fPCLK2 = 30MHz 143.1 ns MHz MHz bit tPCLK s tPCLK s Conditions Min 1 Typ Max Unit tPCLK2 fEXT Timer external clock frequency ResTIM tCOUNTER Timer resolution 16-bit Counter clock period when internal clock is selected TMAX_COUNT Maximum Possible Count 2.3.7 EMI - Memory Interface Subject to general operating conditions for VDD, fHCLK, and TA unless otherwise specified. The tables below use a variable which is derived from the EMI_BCONn registers (described in the STR71x Reference Manual) and represents the special characteristics of the programmed memory cycle. Table 31. Symbol tMCLK tC EMI general characteristics Parameter CPU clock period Memory cycle time wait states Value 1 / fMCLK tMCLK x (1 + [C_LENGTH]) 55/74 Electrical parameters Table 32. Symbol tRCR tRP tRDS tRDH tRAS tRAH tRAT tRRT STR71xF EMI Read Operation Value Parameter Test Conditions Min1) Read to CSn Removal Time Read Pulse Time Read Data Setup Time Read Data Hold Time Read Address Setup Time Read Address Hold Time Read Address Turnaround Time RDn Turnaround Time MCLK=50 MHz 4 wait states 50 pf load on all pins 0.65 1.9 20 tMCLK 19 98 22 0 27 1.5*tM CLK Unit Typ tMCLK tC Max1) 21 100 ns ns ns ns 33 2 3.25 21 ns ns ns ns See Figure 25, Figure 26, Figure 27 and Figure 28 for related timing diagrams. 1. Data based on characterisation results, not tested in production. Table 33. Symbol tWCR tWP tWDS1 tWDS2 tWDH tWAS tWAH tWAT tWWT EMI Write Operation Value Parameter Test Conditions Min1) WEn to CSn Removal Time Write Pulse Time Write Data Setup Time 1 Write Data Setup Time 2 Write Data Hold Time Write Address Setup Time Write Address Hold Time Write Address Turnaround Time WEn Turnaround Time MCLK=50 MHz 3 wait states 50 pf load on all pins 20 77.5 97 77 20 27 0.6 1.75 20 tMCLK Typ tMCLK tC tC + tMCLK tC tMCLK 1.5*tMCLK Max1) 22.5 80 100 80 23 33 3 4.1 23 ns ns ns ns ns ns ns ns ns Unit See Figure 29, Figure 30, Figure 31 and Figure 32 for related timing diagrams. 1. Data based on characterisation results, not tested in production. 56/74 STR71xF Figure 25. Read Cycle Timing: 16-bit READ on 16-bit Memory tRAH Electrical parameters A[23:0] Address tRP RDn tRCR CSn.x WEn.x tRDS tRAS tRDH D[15:0] (Input) Data Input Figure 26. Read Cycle Timing: 32-bit READ on 16-bit Memory tRAT tRAH tRAH A[23:0] Address tRP tRRT Address tRP RDn tRCR CSn.x WEn.x tRAS tRDS tRDH tRDS tRDH D[15:0] (Input) Data Input Data Input See Table 32 for read timing data. Figure 27. Read Cycle Timing: 16-bit READ on 8-bit Memory tRAT tRAH tRAH A[23:0] Address tRP tRRT Address tRP RDn tRCR CSn.x WEn.x tRAS tRDS tRDH tRDS tRDH D[7:0] (Input) Data Input Data Input 57/74 Electrical parameters Figure 28. Read Cycle Timing: 32-bit READ on 8-bit Memory tRAT tRAH tRAH tRAT tRAH tRAT tRAH STR71xF A[23:0] Address tRP tRRT Address tRP tRRT Address tRP tRRT Address tRP RDn tRCR CSn.x WEn.x tRAS tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH D[7:0] (Input) Data Input Data Input Data Input Data Input See Table 32 for read timing data. Figure 29. Write Cycle Timing: 16-bit WRITE on 16-bit Memory tWAH A[23:0] Address RDn tWCR CSn.x tWAS tWP WEn.x tWDS1 tWDH D[15:0] (Output) Data Output Figure 30. Write Cycle Timing: 32-bit WRITE on 16-bit Memory tWAT tWAH tWAH A[23:0] address address RDn tWCR CSn.x tWP tWWT tWP WEn.x tWAS tWDS1 Data Output tWDH tWDS2 Data Output tWDH D[15:0] (Output) See Table 41 for write timing data. 58/74 STR71xF Figure 31. Write Cycle Timing: 16-bit WRITE on 8-bit Memory tWAT tWAH tWAH Electrical parameters A[23:0] address address RDn tWCR CSn.x tWP tWWT tWP WEn.x tWAS tWDS1 Data Output tWDH tWDS2 Data Output tWDH D[7:0] (Output) Figure 32. Write Cycle Timing: 32-bit WRITE on 8-bit Memory tWAT tWAH tWAH tWAT tWAH tWAT tWAH A[23:0] address address address address RDn tWCR CSn.x tWP tWWT tWP tWWT tWP tWWT tWP WEn.x tWAS tWDS1 Data Output tWDH tWDS2 Data Output tWDH tWDS2 Data Output tWDH tWDS2 Data Output tWDH D[7:0] (Output) See Table 33 for write timing data. 59/74 Electrical parameters STR71xF 2.3.8 Communications interfaces I2C - Inter IC Control Interface Subject to general operating conditions for V33, fPCLK1, and TA unless otherwise specified. The STR7 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Note: Restriction: The I/O pins which SDA and SCL are mapped to are not "True" Open-Drain: when configured as open-drain, the PMOS connected between the I/O pin and V33 is disabled, but it is still present. Also, there is a protection diode between the I/O pin and V33. Consequently, when using this I2C in a multi-master network, it is not possible to power off the STR7X while some another I2C master node remains powered on: otherwise, the STR7X will be powered by the protection diode. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 34. I2C Characteristics Standard mode I2C Min tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb Notes: 1. Data based on standard I2C protocol requirement, not tested in production. 2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low 1) Fast mode I2C5) Unit Min 1) 1.3 0.6 100 0 2) 900 3) 300 ns Max 1) s Symbol Parameter Max 1) SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time 4.7 4.0 250 0 3) 1000 20+0.1C b SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time STOP to START condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 300 20+0.1C b 300 0.6 0.6 0.6 1.3 400 400 s s s pF 60/74 STR71xF period of SCL signal. 4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 5. fPCLK1, must be at least 8MHz to achieve max fast I2C speed (400kHz). Electrical parameters 6. The following table gives the values to be written in the I2CCCR register to obtain the required I2C SCL line frequency. Figure 33. Typical Application with I2C Bus and Timing Diagram 4) VDD 4.7k I 2C VDD 4.7k 100 100 SDA SCL BUS STR7 REPEATED START START tsu(STA) SDA tw(STO:STA) START tf(SDA) SCL tr(SDA) tsu(SDA) th(SDA) STOP th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO) Table 35. SCL Frequency Table (fPCLK1=8 MHz.,V33 = 3.3 V) fSCL (kHz) 400 300 200 100 50 20 I2CCCR Value RP=4.7k 83 85h 8Ah 24h 4Ch C4h Legend: RP = External pull-up resistance fSCL = I2C speed NA = Not achievable Note: For speeds around 200 kHz, achieved speed can have 5% tolerance For other speed ranges, achieved speed can have 2% tolerance The above variations depend on the accuracy of the external components used. USB Characteristics The USB interface is USB-IF certified (Low Speed and Full Speed). 61/74 Electrical parameters STR71xF 2.3.9 ADC characteristics Subject to general operating conditions for AVDD, fPCLK2, and TA unless otherwise specified. Table 36. Symbol fMOD VAIN Ilkg PBR SINAD THD ZIN CADC tCONV ADC characteristics Parameter Modulator Oversampling frequency Conversion voltage range 2)3) VIN Standby mode Notes: 1. Unless otherwise specified, typical data are based on TA=25C and AVDD-AVSS=3.3V. They are given only as design guidelines and are not tested. 2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 3. Calibration is needed once after each power-up. 62/74 STR71xF Table 37. ADC Accuracy with fPCLK2 = 20MHz, fADC=10MHz, AVDD=3.3V Parameter Converted code when AIN=0V 1) Conditions Min 2370 1480 1.23 Electrical parameters Symbol ADC_DATA(0V) Typ Max 2565 1680 Unit Decimal code V ADC_DATA(2.5V) Converted code when AIN=2.5V 1) VCM Center voltage of Sigma-Delta Modulator1) Total unadjusted error Differential linearity error1) Integral linearity error 1) 1.25 1.30 TUE |ED| |EL| In this type of ADC, calibration is necessary to correct gain error and offset errors. Once calibrated, the TUE is limited to the ILE. 1.96 2.36 2.19 LSB 3.95 1. Data based on characterisation, not tested in production. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. The effect of negative injection current on robust pins is specified in Section 2.3.5. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 2.3.5 does not affect the ADC accuracy. 63/74 Electrical parameters Figure 34. ADC Accuracy Characteristics STR71xF 4095 4094 4093 (2) (3) (1) Digital Result ADC_DATA Register ADC_DATA(0V) ADC_DATA(2.5V) 5 4 3 2 1 0 1 AVSS 2 3 EL ED 1 LSBIDEAL Out of range 1633 VCM 3100 3101 3102 3103 4093 4094 4095 AVDD VAIN (LSBIDEAL) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 1LSB IDEAL = ----------------------------------------------- AVDD - AVSS 4095 ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Analog Power Supply and Reference Pins The AVDD and AVSS pins are the analog power supply of the A/D converter cell. They act as the high and low reference voltages for the conversion. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see: General PCB Design Guidelines). General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 64/74 STR71xF Electrical parameters 0.1F and optionally, if needed 10pF capacitors as close as possible to the STR7 power supply pins and a 1 to 10F capacitor close to the power source (see Figure 35). The analog and digital power supplies should be connected in a star network. Do not use a resistor, as AVDD is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs near the A/D input being converted. Software Filtering of Spurious Conversion Results For EMC performance reasons, it is recommended to filter A/D conversion outliers using software filtering techniques. Figure 35. Power Supply Filtering STR710 1 to 10F STR7 DIGITAL NOISE FILTERING 0.1F VSS V33 V33 POWER SUPPLY SOURCE (3.3V) EXTERNAL NOISE FILTERING 0.1F AVDD AVSS 65/74 Package characteristics STR71xF 3 3.1 Package characteristics Package Mechanical Data Figure 36. 64-Pin Low Profile Quad Flat Package (10x10) mm Min 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 64 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006 Dim. D D1 A1 A A2 A A1 A2 b 1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008 b c D D1 E1 E e E E1 e c L L1 N L1 h L Number of Pins Recommended footprint (dimensions in mm) 1 66/74 STR71xF Figure 37. 144-Pin Low profile Quad Flat Package Package characteristics Dim. D D1 D3 A1 108 109 73 72 0.08 mm .003 in. b Seating Plane E A A2 mm Min 0.05 1.35 0.17 0.09 1.40 0.22 Typ Max 1.60 Min inches(1) Typ Max 0.063 0.006 0.057 0.011 0.008 A A1 A2 b c D D1 E3 E1 0.15 0.002 1.45 0.053 0.27 0.007 0.20 0.004 21.80 22.00 22.20 0.858 0.867 0.874 19.80 20.00 20.20 0.780 0.787 0.795 17.50 0.689 21.80 22.00 22.20 0.858 0.867 0.874 19.80 20.00 20.20 0.780 0.787 0.795 17.50 0.50 0 0.45 3.5 0.60 1.00 7 0 0.689 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 b D3 E E1 144 1 e 37 36 c L1 E3 e K L h L L1 Number of Pins Jedec Ref. MS-026-BFB N 144 1.Values in inches are converted from mm and rounded to 3 decimal digits. Recommended footprint (dimensions in mm) 67/74 Package characteristics Figure 38. 64-Low Profile Fine Pitch Ball Grid Array Package mm Min 1.210 0.270 1.120 Typ Max Min 0.011 1.700 0.048 STR71xF Dim. A A1 A2 b D D1 E E1 e f ddd N inches Typ Max 0.067 0.044 0.450 0.500 0.550 0.018 0.020 0.022 7.750 8.000 8.150 0.305 0.315 0.321 5.600 5.600 0.220 0.220 7.750 8.000 8.150 0.305 0.315 0.321 0.720 0.800 0.880 0.028 0.031 0.035 1.050 1.200 1.350 0.041 0.047 0.053 0.120 Number of Pins 64 0.005 Figure 39. 144-Low Profile Fine Pitch Ball Grid Array Package mm Min 1.21 0.21 1.12 0.35 0.40 8.80 8.80 0.80 0.60 0.10 0.15 0.08 Number of Pins N 144 Typ Max Min 0.008 0.044 0.45 0.014 0.016 0.018 0.346 0.346 0.031 0.024 0.004 0.006 0.003 1.70 0.048 inches Typ Max 0.067 Dim. A A1 A2 b D D1 E E1 e F ddd eee fff 9.85 10.00 10.15 0.388 0.394 0.400 9.85 10.00 10.15 0.388 0.394 0.400 68/74 STR71xF Package characteristics 3.2 Thermal characteristics The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) Where: (1) TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power. PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the application PI/O < PINT and can be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2 where: K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. Table 38. Symbol (2) (3) Thermal characteristics Parameter Value Unit JA JA JA JA Thermal Resistance Junction-Ambient LQFP 144 - 20 x 20 mm / 0.5 mm pitch Thermal Resistance Junction-Ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch Thermal Resistance Junction-Ambient LFBGA 64 - 8 x 8 x 1.7mm Thermal Resistance Junction-Ambient LFBGA 144 - 10 x 10 x 1.7mm 42 45 58 50 C/W C/W C/W C/W 69/74 Product history STR71xF 4 Product history There are two versions of the STR710F series products. The two versions are functionally identical and differ only with the points listed below. Version "A" was the first version produced and delivered. The second version, version "Z", is currently being phased into production and will replace version "A". Version "Z" has lower power consumption in STOP mode. Marking The difference between the two versions is visible on the marking of the product, with the version letter on top of the part number. This version letter is visible in Figure 40 shows a TQFP144 "A" STR710 and a TQFP64 "Z" STR712 Figure 40. Version Marking A STR710FZ2T6 2208JVG MLT225571 Z STR712FR2 T6 2208JVG MLT225571 Table 39. A and Z version differences Feature A version Z version ARM7TDMI core device Identification (ID) code register (see Version bits [31:28] = 0001 ARM7TDMI Technical Reference Manual) Low power mode consumption in STOP mode at 25 C Not guaranteed Typical 49 A Version bits [31:28] = 0010 50 A maximum at 25C. Less than 30 A at 25 C for 99.730020% of parts 70/74 STR71xF Order codes 5 Order codes Table 40. Order Codes FLASH Kbytes 128+16 256+16 0 128+16 256+16 0 64+16 128+16 256+16 64+16 128+16 256+16 64+16 128+16 256+16 64+16 128+16 256+16 64+16 64+16 RAM Kbyte s 32 64 64 32 64 64 16 32 64 Yes STR711FR0T6 STR711FR1T6 STR711FR2T6 STR712FR0H6 STR712FR1H6 STR712FR2H6 STR712FR0T6 STR712FR1T6 STR712FR2T6 STR715FR0H6 STR715FR0T6 16 32 64 16 No 32 64 Yes 16 No 32 64 16 No 16 LQFP64 10 x 10 LFBGA64 8 x 8 1.7 32 LQFP64 10 x10 LFBGA64 8 x 8 1.7 LQFP64 10x10 No 30 -40 to +85C LFBGA64 8 x 8 1.7 Yes Yes Yes 48 LFBGA144 10 x 10 1.7 Yes Yes Yes 48 LQFP144 20 x 20 EMI USB CAN I/O Ports Package Temp. Range Partnumber STR710FZ1T6 STR710FZ2T6 STR710RZT6 STR710FZ1H6 STR710FZ2H6 STR710RZH6 STR711FR0H6 STR711FR1H6 STR711FR2H6 71/74 Revision history STR71xF 6 Revision history Table 41. Date 17-Mar-2004 05-Apr-2004 08-Apr-2004 15-Apr-2004 Document revision history Revision 1 2 2.1 2.2 First Release Updated "Electrical parameters" on page 32 Corrected STR712F Pinout. Pins 43/42 swapped. PDF hyperlinks corrected. Corrected description of STDBY, V18, VSS18 V18BKP VSSBKP pins Added IDDrun typical data Updated BSPI max. baudrate. Updated "EMI - Memory Interface" on page 55 Corrected Flash sector B1F0/F1 address in Figure 6: Memory Map on page 29 Corrected Table 6 on page 23 LQFP64 TEST pin is 16 instead of 17. Added to TQPFP64 column: pin 7 BOOTEN, pin 17 V33IO-PLL Changed description of JTCK from `External pull-down required' to `External pull-up or pull down required'. Changed "Product Preview" to "Preliminary Data" on page 1 and 3 Renamed `PU/PD' column to `Reset state' in Table 6 on page 23 Added reference to STR7 Flash Programming Reference Manual Added STR715F devices and modified RAM size of STR71xF1 devices Added BGA package in Section 3 Updated ordering information in Section 5. Added PLL duty cycle min and max. in PLL Electrical Characteristics on page 43 Changes 7-Jul-2004 3 29-Oct-2004 4 25-Jan-2005 5 19-Apr-2005 6 72/74 STR71xF Table 41. Date Revision history Document revision history Revision Changes Updated feature description on page 1 Update overview Section 1.1 Added OD/PP to P0.12 in Table 6 Changed name of WFI mode to WAIT mode Changed Memory Map Table 6: Ext. Memory changed to 64 MB and flash register changed to 36 bytes. Added Power Consumption Table 14 Modified BGA144 F3, F5, F12 and G12 in Table 2 and Table 3 Update EMI Timing Table 25 and Figure 29 Added Flashless device. Changed reset state of pins P1.10 and P1.13 from pu to pd, P0.15 from pu to floating and removed x in interrupt column for P1.15 and P1.12 in Table 3 and Table 6 Added notes under Table 3 on EMI pin reset state. Corrected inch value for d3 in Figure 37 Added footprint diagrams in Figure 37 and Figure 39 Updated Section 2: Electrical parameters 13-Oct-2005 7 22-May-2006 8 73/74 STR71xF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 74/74 |
Price & Availability of STR710FBZ2
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |